结型场效应晶体管(简称J-FET)具有低噪声、高输入阻抗以及高截止频率、高输出阻抗的特点。把它做进模拟集成电路里,用于输入级、动态负载和恒流源,可以提高电路的性能。但是,在模拟集成电路里,外延层厚度、扩散深度被双极型晶体管要求所固定。因此,采用一般平面J-FET存在以下二方面的限制: 第一,对J-FET参数的控制,在工艺上比较困难。第二,通常只能把P沟J-FET做进双极型集成电路里,要制造内含N沟低阈值电压的J-FET则是十分困难的。为此,采用了这种新的J-FET结构。它与一般平面的J-FET结构主要不同处是具有V形槽沟道区。顶控制栅沿着V形槽边壁。由于沟道区非 Junction FET (J-FET) with low noise, high input impedance and high cut-off frequency, high output impedance characteristics. Put it into the analog integrated circuit, for the input stage, dynamic load and constant current source, can improve the performance of the circuit. However, in analog integrated circuits, the epitaxial layer thickness and diffusion depth are fixed by the requirements of the bipolar transistor. Therefore, the use of general-purpose planar J-FET has the following two limitations: First, the control of J-FET parameters is technically difficult. Second, the P-channel J-FET can usually only be incorporated into a bipolar integrated circuit. It is very difficult to fabricate a J-FET with a low N-channel threshold voltage. To this end, the use of this new J-FET structure. It differs from the general planar J-FET structure in that it has a V-groove channel region. The top control grid is along the V-groove side wall. Due to channel area non