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为了提高SOI(silicon on insulator)器件的击穿电压,同时降低器件的比导通电阻,提出一种槽栅槽源SOI LDMOS(lateral double-diffused metal oxide semiconductor)器件新结构.该结构采用了槽栅和槽源,在漂移区形成了纵向导电沟道和电子积累层,使器件保持了较短的电流传导路径,同时扩展了电流在纵向的传导面积,显著降低了器件的比导通电阻.槽栅调制了漂移区电场,同时,纵向栅氧层承担了部分漏极电压,使器件击穿电压得到提高.借助2维数值仿真软件MEDICI详细分析了器件的击穿特性和导通电阻特性.仿真结果表明:在保证最高优值的条件下,该结构的击穿电压和比导通电阻与传统SOI LDMOS相比,分别提高和降低了8%和45%.
In order to improve the breakdown voltage of silicon on insulator (SOI) devices and reduce the specific on-resistance of the device, a new structure of SOI LDMOS (lateral double-diffused metal oxide semiconductor) The gate and the trench source form a vertical conduction channel and an electron accumulation layer in the drift region to keep the device short in the current conduction path and extend the conduction area of the current in the longitudinal direction and significantly reduce the specific on-resistance of the device. The trench gate modulates the electric field in the drift region and at the same time, the vertical gate oxide layer takes part of the drain voltage and the breakdown voltage of the device is increased. The breakdown characteristics and on-resistance characteristics of the device are analyzed in detail with the aid of the 2-D numerical simulation software MEDICI. The simulation results show that the breakdown voltage and on-resistance of the structure increase and decrease by 8% and 45% respectively compared with the traditional SOI LDMOS under the condition of the highest optimal value.