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介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法。合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标。封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输。封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径。
This paper introduces the characteristics of digital-analog hybrid high-speed integrated circuit (IC) package and the general analysis methods of collaborative design of such package. Reasonable and effective substrate design is an important guarantee to achieve reliable packaging. Based on the idea of physical interconnect design and electrical design collaboration, Cadence APD tools and 3D electromagnetic field simulation tools are used to implement specific digital-analog hybrid high-speed integrated circuits Out circuit) package design and simulation demonstration, chip packaging assembly test, the detector system performance is good, package design to achieve the desired goal. Package Electrical Simulation Mainly includes: Package Signal Transmission Channel S-Parameter Extraction, Power / Ground Network Evaluation, Probe Readout Chip Package The interconnect channel is designed to handle high-speed signals with a signal bandwidth of 350 MHz (or a signal rise time greater than 1 ns) The transmission. Collaborative analysis of package substrate layout design and substrate electrical design is an effective way to improve the design efficiency of digital-analog hybrid high-speed integrated circuit package.