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目的:针对低电压下传统SRAM灵敏放大器控制时序受工艺、温度变化而引起的较大的控制时序的波动,设计一种基于多级双复制位线延迟技术的控制时序产生电路。创新点:同时采用多级和双复制位线技术,充分发挥两者在降低控制时序变化方面的优点,取得整体上的改进。方法:首先,分析现有复制位线延迟技术,从统计学角度对各技术之间的关系进行分析,进而提出一种基于多级双复制位线延迟技术的控制时序产生电路(图5)。然后,针对所提电路与现有技术在最差条件下进行蒙特卡洛仿真对比,得出所提技术在最差工作条件下,与现有技术相比具有更好的鲁棒性(图8)。最后在电压、工艺角以及温度分别变化时,对所提电路设计与现有的电路进行性能对比,得出在工艺、电压及温度变化时,所提电路具有更好的稳定性(图9-11)。结论:针对低电压SRAM灵敏放大器控制时序在工艺、电压以及温度变化产生的波动,提出一种多级双复制位线延迟技术,实现进一步降低灵敏放大器控制时序波动的效果。
OBJECTIVE: To control the fluctuation of the control timing caused by the process and temperature changes of the conventional SRAM sense amplifier under low voltage, a control timing generation circuit based on multilevel double-copy bit line delay technology is designed. Innovation: At the same time using multi-level and double-copy bit line technology, give full play to both the advantages of reducing control timing changes, and achieved overall improvement. Methods: Firstly, we analyze the existing techniques of bit line delay replication and analyze the relationship among the techniques from a statistical point of view. Then, we propose a control timing generation circuit based on the multi-level double-copy bit line delay technique (Figure 5). Then, comparing the proposed circuit with the prior art under the worst-case Monte Carlo simulation, it is concluded that the proposed technique has better robustness under the worst working conditions compared with the prior art (FIG. 8 ). Finally, when the voltage, the process angle and the temperature change respectively, the proposed circuit is compared with the existing circuit to get the better stability of the circuit when the process, voltage and temperature change (Figure 9- 11). Conclusion: Aiming at the fluctuations of process, voltage and temperature in the control sequence of the low-voltage SRAM sense amplifier, a multilevel double-copy bit-line delay technique is proposed to further reduce the effect of the timing-sensitive fluctuation of the sense amplifier.