Mentor公司最近发布SST Velocity,以继续致力于超亚微米静态时序分析。由Mentor公司专门开发的SST Velocity基于一种前沿算法,该算法解决了复杂超亚微米ASIC验证带来的新的不同的问题。通过提供易于使用、性能优异及满足现有方案无法解决的市场需求的工具,SST Velocity使静态时序分析成为了主流。 SST Velocity是市场上第一个提供增强分析能力的工具,该能力给设计者带来了许多好处。它允许交互的“What-if”电路分析,最小化了特性描述的时间, Mentor recently unveiled SST Velocity to continue its commitment to ultra-submicron static timing analysis. SST Velocity, developed specifically by Mentor, is based on a cutting-edge algorithm that addresses the new and different issues associated with complex sub-micron ASIC verification. SST Velocity has made static timing analysis the mainstream by providing tools that are easy to use, perform well and meet the market demands that existing solutions can not solve. SST Velocity is the first on the market to provide enhanced analysis capabilities that bring many benefits to designers. It allows interactive “What-if” circuit analysis to minimize the time characterization,