论文部分内容阅读
详细研究了一种基于薄埋氧层及三层顶层硅衬底(Triple-Layer Top Silicon,TLTS)的SOI高压LDMOS器件。该结构在SOI介质层上界面的顶层硅内引入一高浓度n+层,当器件处于反向阻断状态时,高浓度n+区部分耗尽,漏端界面处已耗尽n+层内的高浓度电离施主正电荷可增强介质层电场,所产生的附加电场将调制漂移区内的电场,防止器件在漏端界面处被提前击穿,从而可在较薄的埋氧层(BOX)上获得较高耐压。在0.4μm BOX上获得了624V的耐压。与几种SOI器件相比,所提出的TLTS LDMOS器件具有较高优值(FOM)。
A SOI high-voltage LDMOS device based on a thin buried oxide layer and a triple-layer top silicon (TLTS) substrate is investigated in detail. The structure introduces a high-concentration n + layer into the top silicon of the SOI dielectric layer interface. When the device is in the reverse blocking state, the high-concentration n + region is partially depleted and the high-concentration The positive charge of the ionization donor can enhance the electric field of the dielectric layer, and the additional electric field generated will modulate the electric field in the drift region to prevent the device from being prematurely breakdown at the drain-end interface so that the device can be fabricated on a thinner buried oxide (BOX) High voltage. A withstand voltage of 624 V was obtained on the 0.4 μm BOX. The proposed TLTS LDMOS device has a higher figure of merit (FOM) than several SOI devices.