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白行设计的用于频率测量的ＡＳＩＣ采用白顶向下的设计方法，用ｖｅｒｉｌｏｇ语言建模，使用ｃａｄｅｎｃｅｖｅｒｉｌｏｇ仿真工具，保证了芯片具有可靠的性能和精度，同时设计周期也大为缩短。
The white-line ASIC designed for frequency measurement uses a white-on-white design approach, modeling in verilog language and using cadenceverilog simulation tools to ensure reliable performance and accuracy of the chip with dramatically shortened design cycles.