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在可编程逻辑器件(PLD)领域,虽然人们较多地关注大型、复杂、基于查表的现场可编程门阵列(FPGA),同时有越来越多的设计采用基于乘积项的CPLD器件来实现控制逻辑、逻辑译码和组合逻辑等功能。在需要实现非常高速的逻辑功能或者不允许在上电期间配置逻辑(由于定时或其它因素)的场合,设计人员都会首选CPLD。此外,大部分CPLD的软件相对容易获得,通常可通过供货商的网站下载,而且能够相对快捷地完成设计并满足性能的需要。 CPLD供应商正逐渐地改进这些乘积项器件的制造工艺。目前,Altera已经开始供应采用0.22微米、四层金属布线工艺、芯核工作电压为
In the field of programmable logic devices (PLDs), although people pay more attention to large, complex, table-based field-programmable gate arrays (FPGAs), more and more designs adopt CPLD devices based on product terms Control logic, logic decoding and combinational logic functions. Designers are the CPLDs of choice when it comes to implementing very high-speed logic functions or not allowing logic to be configured during power-up (due to timing or other factors). In addition, most CPLD software is relatively easy to obtain, and is usually downloadable from the supplier’s website, and can be designed relatively quickly and meet performance needs. CPLD suppliers are gradually improving the manufacturing processes for these product terms. Currently, Altera has begun to supply the use of 0.22 micron, four metal wiring process, the core operating voltage