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设计了一个应用于18位高端音频模数转换器(ADC)的三阶低功耗ΣΔ调制器.调制器采用2-1级联结构,通过优化调制器系数来提高其动态范围,并减小调制器输出频谱中的杂波.电路设计中采用栅源自举技术实现输入信号采样开关,有效提高了采样电路的线性度;提出一种高能效的A/AB类跨导放大器,在仅消耗0.8mA电流的情况下,达到100V/μs以上的压摆率.针对各级积分器不同的采样电容,逐级对跨导放大器进行进一步功耗优化.调制器在中芯国际0.18μm混合信号CMOS工艺中流片,芯片核心面积为1.1mm×1.0mm.测试结果表明在22.05kHz带宽内,信噪失真比和动态范围分别达到91dB和94dB.在3.3V电源电压下,调制器功耗为6.8mW,适合于高性能、低功耗音频模数转换器应用.
A third-order, low-power ΣΔ modulator designed for an 18-bit high-end audio analog-to-digital converter (ADC) is designed.The modulator uses a 2-1 cascade architecture to increase its dynamic range by optimizing the modulator coefficients and to reduce Modulator output spectrum of the clutter circuit design using gate-source bootstrap technology to achieve input signal sampling switch, effectively increasing the linearity of the sampling circuit; proposed an energy-efficient A / AB transconductance amplifier class, only consume 0.8mA current case, reaching more than 100V / μs slew rate.According to the different levels of the integrator sampling capacitor, step by step on the transconductance amplifier for further power optimization.Modulator in the SMIC 0.18μm mixed-signal CMOS Process chip, chip core area of 1.1mm × 1.0mm.The test results show that within the 22.05kHz bandwidth, the signal to noise ratio and dynamic range of 91dB and dynamic range respectively 91V power supply voltage, the modulator power consumption of 6.8mW , Suitable for high performance, low power audio analog-to-digital converter applications.