论文部分内容阅读
文章针对典型的32位浮点乘法器,对Booth算法产生的部分积重新分组,采用CSA和4-2压缩器的混合电路结构,对传统的Wallace树型乘法器进行改进,并提出一种高速的树型乘法器阵列结构。该结构与传统的Wallace树型相比,具有更小的延时、更规整的布局布线,使其更易于VLSI实现。
Aiming at the typical 32-bit floating-point multiplier, the article regroups the partial products generated by Booth algorithm. Using the hybrid circuit structure of CSA and 4-2 compressor, this paper improves the traditional Wallace tree multiplier and proposes a high speed Tree-type multiplier array structure. Compared with the traditional Wallace tree, the structure has smaller delay and more regular placement and routing, which makes it easier to VLSI implementation.