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A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.
A new structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator (BOX) in an SOI device is split into two sections: the source-section BOX and A highly-doped Si layer, referred to as a non-depletion potential-clamped layer (NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes , the blocking voltage (BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical of the new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semic (LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance (Ron, sp) is reduced by 69% in comparison to the conventional structure.