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针对数模混合结构的电荷泵锁相环电路,建立了系统的数学模型,确定了电荷泵锁相环的系统参数,提出一种能够有效消除时钟馈通、电荷注入等非理想特性影响,并具有良好电流匹配特性的电荷泵电路,以及一种中心频率可调的压控振荡器电路。电路采用SMIC 0.18μm CMOS工艺模型,使用Spectre进行仿真。结果显示,整个锁相环系统的功耗约为40 mW,输出时钟信号峰-峰值抖动为21 ps@2.5 GHz,单边带相位噪声在5 MHz频偏处为-105 dBc/Hz。
Aiming at the charge-pump phase-locked loop circuit of digital-analog mixed structure, a mathematical model of the system is established, the system parameters of the charge-pump phase-locked loop are determined, and a non-ideal characteristic such as clock feedthrough and charge injection is effectively eliminated A charge pump circuit with good current matching characteristics, and a voltage-controlled oscillator circuit with adjustable center frequency. The circuit uses a SMIC 0.18μm CMOS process model and a Specter simulation. The results show that the entire PLL system consumes about 40 mW, the output clock signal has a peak-to-peak jitter of 21 ps@2.5 GHz and the single-sideband phase noise is -105 dBc / Hz at a 5 MHz offset.