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分析了半导体器件静态漏电对高可靠设备造成的危害。对比了失效器件在不同偏压条件下的测试结果,结合器件芯片版图的设计特点以及制造工艺特点,对隔离型达林顿管静态漏电的失效现象进行了分析,通过故障树分析,排除了外部沾污、静电损伤、过电应力损伤等使用问题导致器件失效的可能性,提出了器件出现异常静态漏电流是因为采用扩散方法制作的pn结深度不足导致的假设,并利用磨角染色法证明了失效芯片隔离岛隔离墙pn结深度不足的假设,并提出了改进意见。
Analysis of the static leakage of semiconductor devices on high-reliability equipment caused harm. By comparing the test results of failed devices under different bias conditions and analyzing the design features of the device chip layout and the characteristics of the manufacturing process, the failure phenomenon of isolated Darlington static leakage is analyzed. Fault tree analysis excludes the external Stray, electrostatic damage, over-electric stress damage and other use problems lead to the possibility of failure of the device. It is proposed that the abnormal static leakage current of the device is due to the assumption of insufficient depth of pn junction made by diffusion method. The failure of chip isolation island wall pn junction depth of hypotheses and made improvements.