论文部分内容阅读
随着数字电路向更高速度发展,设计人员必须将印制电路板上的每一根印制连线都当成一根射频传输线来处理。在这些射频传输线中,你要努力保持线路阻抗Z_0为一恒定值—一般为50Ω,并以相同阻抗端接线路。数字电路系列,如ECL、PECL和LVDS,都在称为平衡传输线的一对印制线上传输数据。一根传输线转换到高电平,而另一根传输线则转换到低电平。如同其他高速逻辑电路系列那样, 你必须保持传输线线路阻抗恒定不变,并使传输线端接合适。如果两根印制线之间的间距很大, 你可以把印
As digital circuits evolve to higher speeds, designers must treat each printed connection on a printed circuit board as a radio frequency transmission line. In these RF transmission lines, you should try to keep the line impedance Z_0 constant - typically 50Ω and terminate the line with the same impedance. Digital circuit families such as ECL, PECL, and LVDS all transmit data over a pair of traces, called balanced transmission lines. One transmission line is switched high while the other transmission line is switched low. As with other high-speed logic circuits, you have to keep the transmission line impedance constant and adapt the transmission line termination. If the distance between two printed lines is large, you can print