结合流水线技术,对一种新提出的RS译码的欧几里德迭代算法及其VLSI结构,给出了基于时域译码的FPGA实现和验证,并采用分时复用技术对译码器的关键模块——解关键方程模块的结构加以改进,使其错误位置和错误值多项式单元能面积复用。该结构的特点是:控制单元简单;模块结构非常规则,易于用VerilogHDL实现;可应用于高速通信场合。 Combined with the pipeline technology, a new proposed Euclidean iterative algorithm for RS decoding and its VLSI structure is given FPGA implementation and verification based on time-domain decoding, and the use of time-sharing multiplexing decoder The key module - the solution to the key equation module structure to be improved, so that its error location and error value polynomial cells can reuse area. The structure is characterized by: the control unit is simple; module structure is very regular, easy to achieve with VerilogHDL; can be used in high-speed communications applications.