采用IBM0.13μm CMOS工艺,设计了适用于80MS/s流水线结构A/D转换器的比较器。电路使用全差分动态锁存结构,在Lewis-Gray结构的基础上,保留比较器阈值和输入差分管尺寸之间的线性比例关系,改进复位和输出电路结构,降低了设计复杂度和功耗,减小了面积。通过细致的版图考虑,实现了7种不同阈值电压的比较器,失调小于13mV,最大面积为25μm×13μm,最高工作频率达500 MHz;80MS/s工作时,功耗最大仅为63μW,低于Lewis-Gray结构的比较器。 Using IBM0.13μm CMOS technology, designed for 80MS / s pipeline structure A / D converter comparator. Based on the Lewis-Gray structure, the circuit retains the linear proportion between the comparator threshold and the input differential transistor size, improves the structure of the reset and output circuits, reduces the design complexity and power consumption, Reduce the area. Through careful layout considerations, seven comparators with different threshold voltages are realized, with an offset of less than 13mV, a maximum area of ​​25μm × 13μm and a maximum operating frequency of 500 MHz. At 80MS / s operation, the maximum power dissipation is only 63μW, Lewis-Gray structure of the comparator.