论文部分内容阅读
本文介绍短沟道Si—栅MOS大规模集成电路的一种新的制造工艺技术。该工艺技术的特点在于用两个单一的磷扩散工艺,形成源和漏区并把磷扩散进多晶硅。其特点也在于在掺磷和非掺磷多晶硅之间所用的腐蚀速率不同。前者降低多晶硅电阻而与结深无关,并对用多晶硅互连的高速MOS大规模集成电路有效。后者提供多晶硅的精确和均匀的图形结构,它对良好的阈值电压的控制能力和均匀性有效,因为对低于3μm的沟道长度是灵敏的。本文同普通工艺进行了比较,为降低多晶硅电阻而检测了工艺效应。并通过用本工艺制造的短沟道晶体管的阈值电压分布,为多晶硅的精确和均匀的图形结构而检测工艺效应。考虑到边缘效应,为说明精确和均匀的图形结构,示出了多晶硅样品的腐蚀剖面图。
This article describes a new manufacturing process technology for short-channel Si-gate MOS LSIs. This process technology is characterized by two single phosphor diffusion processes to form source and drain regions and to diffuse phosphorus into polysilicon. It is also characterized by the different etch rates used between phosphorus-doped and non-phosphorus-doped polysilicon. The former reduces polysilicon resistance but has nothing to do with junction depth and is effective for high speed MOS LSIs interconnected with polysilicon. The latter provides an accurate and uniform pattern of polysilicon that is effective for good threshold voltage control and uniformity as it is sensitive to channel lengths below 3 μm. This article is compared with the conventional process, in order to reduce the polysilicon resistance and detect the process effect. And the process effect is detected for the precise and uniform pattern structure of polysilicon through the threshold voltage distribution of the short channel transistors made using the present process. In view of the edge effect, an etching profile of the polysilicon sample is shown to illustrate the precise and even pattern structure.