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提出了一种应用于浮点加法器设计中前导1预判电路(LOP)的实现方案。此方案的提出是针对进行浮点加减运算时,尾数相减的结果可能会产生若干个头零,对于前导1的判断将直接影响规格化左移的位数而提出的。前导1的预判与尾数的减法运算并行执行,而不是对减法结果的判断,同时,并行检测预判中可能产生的1位误差,有效缩短了整个加法器的延时。LOP电路设计采用VHDL语言门级描述,已通过逻辑仿真验证,并在浮点加法器的设计中得到应用。
A scheme of Preamble 1 predictor (LOP) used in floating-point adder design is proposed. This scheme is proposed for floating-point addition and subtraction operations, the result of the mantissa subtraction may produce a number of head zero, the decision for the leading 1 will directly affect the normalized left shift of the number of proposed. The preamble of the leading 1 and the subtraction of the mantissa are executed in parallel instead of the judgment of the subtraction result. Simultaneously, the 1-bit error that may be generated in the parallel detection pre-judgment effectively shortens the delay of the entire adder. LOP circuit design using VHDL language gate-level description, has been verified by the logic simulation and floating-point adder in the design of the application.