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随着CMOS工艺尺寸不断缩小,尤其在65nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。
As CMOS process sizes continue to shrink, negative bias temperature instability (NBTI) has become a key factor in the reliability of CMOS devices, especially in CMOS processes at 65 nm and below. Based on the framework of NBTI’s static timing analysis, a logic gate based on NBTI’s prioritized logic gate is prioritized, taking into account the gate-path dependencies in common Positioning the key. The experiment of ISCAS reference circuit in 45nm CMOS process shows that compared with similar methods, under the same experimental conditions, this method not only has fewer key gates, but also has a higher improvement rate of delay for critical paths , Effectively reducing the design overhead.