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首次在国内成功地制作了栅长为 70 nm的高性能 CMOS器件 .为了抑制 70 nm器件的短沟道效应同时提高它的驱动能力 ,采用了一些新的关键工艺技术 ,包括 3nm的氮化栅氧化介质 ,多晶硅双栅电极 ,采用重离子注入的超陡倒掺杂沟道剖面 ,锗预无定形注入加低能注入形成的超浅源漏延伸区 ,以及锗预无定形注入加特殊清洗处理制备薄的、低阻自对准硅化物等 . CMOS器件的最短的栅长 (即多晶硅栅条宽度 )只有 70 nm,其 NMOS的阈值电压、跨导和关态电流分别为 0 .2 8V、 490 m S/m和 0 .0 8n A/μm ;而 PMOS阈值电压、跨导和关态电流分别为- 0 .3V、 34 0 m S/m m和 0 .2 n A /μm .并研制成功了 10 0 nm栅长的 CMOS 5 7级环形振荡器 ,其在 1.5 V、 2 V和 3V电源电压下的延迟分别为 2 3.5 ps/级、 17.5 ps/级和 12 .5 ps/级
For the first time in China, a high-performance CMOS device with a gate length of 70 nm was successfully fabricated. In order to suppress the short-channel effect of a 70 nm device and improve its driving ability, some new key process technologies were adopted, including a 3 nm nitride gate Oxide medium, polysilicon double gate electrode, ultra-steep down-doped channel with heavy ion implantation, germanium pre-amorphous injection plus ultra-shallow source-drain extension formed by low energy implantation, and pre-amorphous germanium implantation with special cleaning treatment Thin, low-resistance self-aligned silicide, etc. The shortest gate length (ie, polysilicon gate width) of a CMOS device is only 70 nm with a threshold voltage of NMOS, a transconductance, and an off-state current of 0.8V, 490 m S / m and 0.08 n A / μm, respectively; while the threshold voltage of PMOS, the transconductance and the off-state current are -0.3V, 3400 mS / mm and 0.2 nA / μm, respectively. 10 5 nm CMOS 5 7-stage ring oscillator with gate delays of 2 3.5 ps / level, 17.5 ps / level and 12.5 ps / level at 1.5 V, 2 V and 3 V supplies respectively