论文部分内容阅读
在分析边界扫描测试技术的工作机制对测试主控系统的功能需求基础上,提出了一种基于PCI总线采用FPGA实现的低成本边界扫描测试主控器的硬件设计方案.该系统以PC机为平台,利用FPGA器件设计实现JTAG主控芯核,并在主控器芯核内加入FIFO,提高了PCI总线的传送速率,使用户能够利用计算机方便的组成一个边界扫描测试系统.经仿真和测试实践表明,该系统产生的测试信号完全满足IEEE1149.1协议的时序要求,对支持IEEE1149.1协议的芯片进行功能测试和PCB板的互连测试及电路故障诊断.该系统结构简单,使用方便,工作可靠.
Based on the analysis of the working mechanism of the boundary scan test technique to the functional requirements of the test main control system, a hardware design scheme of a low cost boundary scan test host based on PCI bus is proposed. The system uses a PC Platform, using FPGA device design to achieve JTAG master core, and in the master core into the FIFO to improve the PCI bus transfer rate, so that users can use the computer to facilitate the formation of a boundary-scan test system. Simulation and testing Practice shows that the test signal generated by the system fully meets the timing requirements of the IEEE1149.1 protocol and performs functional testing and PCB interconnection testing and circuit fault diagnosis on the chips supporting the IEEE1149.1 protocol.The system is simple in structure and easy to use, Reliable work.