论文部分内容阅读
本文介绍一个高速16K位动态MOS随机存储器(RAM)的方案。这个存储器采用了先进的n沟道硅栅MOS工艺(5μm 光刻技术)制成的面积为22×36μm~2的单管单元。设计的主要特点是采用一个具有高速度(读取时间为200ns)和低功耗(400ns 周期内为600mw)的读出线路图。全译码存储器制在5×7mm~2的芯片上,并装配在22引线陶瓷的双列直插式封装内。
This article describes a high-speed 16K-bit dynamic MOS random access memory (RAM) program. The memory uses an advanced n-channel silicon gate MOS process (5μm lithography) made of an area of 22 × 36μm ~ 2 single-tube unit. The main feature of the design is the use of a readout with high speed (200ns read time) and low power consumption (600mW in 400ns cycle). The whole decoder memory system in 5 × 7mm ~ 2 chip, and assembled in the 22-lead ceramic dual in-line package.