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随着集成电路工艺水平的不断提高、器件尺寸的不断缩小以及电源的不断降低,传统的锁存器越发容易受到由辐射效应引起的软错误影响。为了增强锁存器的可靠性,提出了一种适用于低功耗电路的自恢复SEU加固锁存器。该锁存器由传输门、反馈冗余单元和保护门C单元构成。反馈冗余单元由六个内部节点构成,每个节点均由一个NMOS管和一个PMOS管驱动,从而构成自恢复容SEU的结构。在45nm工艺下,使用Hspice仿真工具进行仿真,结果表明,与现有的加固方案FERST[1]结构相比,在具备相同面积开销和单粒子翻转容忍能力的情况下,提出的锁存器不仅适用于时钟门控电路,而且节省了61.38%的功耗-延迟积开销。
As the level of integrated circuit technology continues to increase, the ever-shrinking device size and the ever-decreasing power supply, traditional latches are more susceptible to soft errors caused by radiation effects. In order to enhance the reliability of the latch, a self-recovery SEU hardened latch suitable for low-power circuits is proposed. The latch consists of transmission gate, feedback redundancy unit and protection gate C unit. The feedback redundancy unit is composed of six internal nodes, each of which is driven by an NMOS transistor and a PMOS transistor to form a self-recovery SEU structure. Under the 45nm process, the Hspice simulation tool is used to simulate. The results show that compared with the existing FERST [1] structure, the proposed latch not only has the same area overhead and single-particle rollover capability Suitable for clock gating circuit, and save 61.38% of the power - delay product plot.