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提出一种可兼容V1.3版本规范的低时延端点实现方案。在该方案中,输出和输入路径上的多数模块工作在直通模式以产生稳定的低时延。对于事务接口,请求和响应可以通过不同的用户定义端口输入并共享传输路径,而且同时发起的事务能在安全的仲裁机制下保持有序传送。为了防止无效的数据传输,废弃的事务包将会被改进的4队列式缓冲模块撤销。对于串行物理接口,1x/4x链路能为事务包和控制符号提供可靠的数据传送,并实现流量控制、错误检测及恢复等关键的链路管理功能。与参考设计相比,此方案能获得更低的传输时延和更高的数据吞吐率。此方案的功能和性能已通过FPGA平台的验证,因此能满足下一代高速嵌入式互连的应用需求。
A scheme of low latency endpoint compatible with V1.3 version is proposed. In this scenario, most modules on the output and input paths operate in pass-through mode to produce a stable low-latency. For transactional interfaces, requests and responses can be entered through different user-defined ports and shared over the transmission path, and concurrently initiated transactions can be kept in an orderly delivery under a secure arbitration mechanism. To prevent invalid data transfers, discarded transaction packages will be revoked by the improved 4-queue buffer module. For serial physical interfaces, 1x / 4x links provide reliable data transfer for transactional packets and control symbols and enable critical link management functions such as flow control, error detection and recovery. Compared with the reference design, this scheme can achieve lower transmission delay and higher data throughput. The functionality and performance of this solution has been verified by the FPGA platform to meet the application requirements of the next generation of high-speed embedded interconnects.