数字抽取滤波器在∑△(Sigma-delta)ADC芯片中占据了大部分的面积,为了减小芯片的面积,通过提高CIC(Cascade Integrator Comb)滤波器的降采样倍数,在整体设计中少用了1个半带滤波器,在达到相同设计目标的情况下,比使用传统结构进行设计的滤波器少用了57个乘法器、56个加法器以及61个状态寄存器,有效地减小了芯片的使用面积. Digital decimation filters occupy most of the area in a sigma-delta ADC chip. To reduce the chip area, it is less useful in the overall design by increasing the down sampling multiplier of the CIC (Cascade Integrator Comb) filter With a half-band filter, 57 multipliers, 56 adders, and 61 status registers were used less than the filter designed with the conventional structure, achieving the same design goals, effectively reducing the number of chips The use of area.