论文部分内容阅读
针对无线传感器网络节点芯片的小面积、低功耗要求,基于SHA-1算法提出了一种具有全折叠结构的硬件实现方法.通过折叠数据通路的方式,降低了面积开销;同时还通过采用进位跳跃加法器(CSKA)优化关键路径的方式,提高了电路的整体工作性能.在SMIC 0.35μm CMOS工艺条件下,设计的SHA-1模块其实现面积比目前已知最小的SHA-1实现方法减小了20.22%,功耗降低了15.96%,而电路的工作频率则提高了33.74%.分析结果表明,该硬件模块完全适用于无线传感器网络节点芯片的应用环境.
Aiming at the demand of small area and low power consumption of wireless sensor network node chip, a hardware implementation method with full-folding structure is proposed based on SHA-1 algorithm. By folding the data path, the area overhead is reduced. At the same time, (CSKA) to optimize the critical path and improve the overall performance of the circuit.When SMIC 0.35μm CMOS process conditions, the design of the SHA-1 module to achieve the area than the currently known minimum SHA-1 method to reduce 20.22% smaller, 15.96% lower power consumption and 33.74% higher circuit operating frequency.The analysis results show that the hardware module is fully suitable for wireless sensor network node chip application environment.