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对一款75V功率场效应管失效芯片进行了分析。通过TCAD软件进行数值仿真,验证失效原因。在终端长度不变的前提下,获得具有两个场限环的终端结构,基本满足电场可靠性小于2.5×105 V/cm的要求。设计了三个场限环终端结构,击穿电压提高至94.7V,硅表面最大电场为2.17×105 V/cm,小于临界电场2.2×105 V/cm,降低了最大碰撞电离率,提高了器件的可靠性。
A 75V power FET failure chip was analyzed. TCAD software for numerical simulation to verify the cause of failure. Under the premise of constant terminal length, a terminal structure with two field limiting rings is obtained, which basically meets the requirement that the electric field reliability is less than 2.5 × 10 5 V / cm. Three field limiting ring termination structures were designed. The breakdown voltage increased to 94.7V. The maximum electric field of silicon surface was 2.17 × 105 V / cm, less than the critical electric field of 2.2 × 105 V / cm, which reduced the maximum impact ionization rate and improved the device The reliability.