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为了解决10G以太网接入系统中ATM通用测试及操作物理层接口(UTOPIA接口)的设计问题,提出了并行状态机的设计方法。讨论了10G以太网接入系统的整体结构和接口设计。提出了求L-并行状态机的可达状态集、状态转移表、状态序列集以及动作表的算法。并以这些算法为基础,讨论了L-并行状态机的设计复杂度问题。以此方法为基础,设计了两路并行的10G以太网接入系统的UTOPIALevel-4接口,使芯片所需的工作时钟频率降低了一半,从而证明此方法可以有效地应用于并行状态机的设计。
In order to solve the design problem of ATM universal testing and operation of the physical layer interface (UTOPIA interface) in the 10G Ethernet access system, a design method of the parallel state machine is proposed. Discussed the overall structure and interface design of 10G Ethernet access system. An algorithm of seeking reachable state set, state transition table, state sequence set and action table of L-parallel state machine is proposed. Based on these algorithms, the design complexity of L-parallel state machine is discussed. Based on this method, a two-way UTOPIALevel-4 interface of 10G Ethernet access system is designed, which reduces the working clock frequency required by the chip in half, which proves that this method can be effectively applied to the design of parallel state machine .