仿真贯穿于ASIC设计的各个阶段中,是ASIC设计过程中使用的最多的工具。作为专业开发Verilog仿真技术的Viewlog Chronologic分部,从1992年推出第一代Verilog仿真器时起,到现在已更新了三代,近十个版本,成为ASIC设计中贯穿整个过程的理想仿真器。提供了包括模型开发,交互调试,回归测试及Sign-off中所需的所有能力。 Simulation runs through all phases of ASIC design and is the most used tool in ASIC design. The Viewlog Chronologic division, which specializes in Verilog simulation technology, has been updated to three generations and nearly ten versions since the first-generation Verilog simulator was introduced in 1992, making it an ideal simulator throughout ASIC design. Provides all the capabilities required for model development, interactive debugging, regression testing, and Sign-off.