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采用三维封装结构取代传统的平面封装结构可获得高性能集成电力电子模块.在实验室完成由2只芯片尺寸封装MOSFET和驱动、保护等电路构成的三维封装半桥IPEM.从互连焊点形状的优化和封装工艺过程参数的控制出发,进行IPEM的可靠性控制.采用阻抗分析仪Agilent 4395A测量IPEM的寄生参数,建立了半桥IPEM的寄生参数模型;采用半桥IPEM构成12V/3A输出的同步整流Buck变换器,2只MOSFET的漏源极尖峰电压小,说明HB-IPEM的三维封装结构有效减小了寄生电感.运用Flotherm软件对半桥IPEM进行了热分析,给出了温度分布仿真结果.焊料凸点传热使芯片的最高结温明显降低,三维封装结构实现了良好的热设计.
A three-dimensional packaging structure is adopted to replace the traditional planar packaging structure to obtain a high-performance integrated power electronic module, and a three-dimensional packaged half-bridge IPEM, which is composed of two MOSFETs and a driving and protection circuit, is completed in a laboratory. And control the process parameters of the package, the reliability of IPEM was controlled.The parasitic parameters of the IPEM were measured by the impedance analyzer Agilent 4395A, and the parasitic parameter model of the half-bridge IPEM was established. The half-bridge IPEM was used to form the 12V / 3A output Simultaneously rectified Buck converter, the leakage current spikes of the two MOSFETs are small, which shows that the three-dimensional packaging structure of HB-IPEM effectively reduces the parasitic inductance.The thermal analysis of the half-bridge IPEM is carried out by Flotherm software, and the temperature distribution simulation Results. Solder bump heat transfer significantly lower the maximum junction temperature of the chip, the three-dimensional package structure to achieve a good thermal design.