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给出了一种应用于高速流水线A/D转换器的数字延迟锁相环电路。该电路的锁定过程采用顺序查找算法,设计了锁定检测窗口,用来判断延迟后的输出时钟信号是否满足锁定条件,根据检测结果即时调整延时大小,能有效避免误锁现象,准确完成延迟锁相功能。该数字延迟锁相环采用SMIC 0.18μm 1.8VCMOS工艺实现,频率范围为40～250MHz。在输入最大频率下,仿真的锁定时间约为690ns,抖动约为1.5ps。
A digital delay PLL is proposed for high speed pipeline A / D converter. The circuit locking process using sequential search algorithm designed lock detection window, used to determine whether the delayed output clock signal to meet the lock condition, according to the detection results to adjust the delay size, can effectively avoid the phenomenon of false lock, accurate completion of the delay lock Phase function. The digital delay PLL using SMIC 0.18μm 1.8VCMOS technology to achieve the frequency range of 40 ~ 250MHz. At the maximum input frequency, the simulation’s lock-up time is about 690ns and the jitter is about 1.5ps.