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研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μmCMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.
Developed a compact direct digital frequency synthesizer (DDFS) for high-accuracy Rubidium frequency-tag SoC implementation.In order to reduce the chip area and reduce power consumption, the use of sinusoidal symmetry technology, modified Sunderland technology, sine phase difference technology, Four-wire approximation technique and quantization and error ROM techniques to compress the phase-to-sinusoidal mapping data. With these techniques, the ROM size is reduced by 98% using a standard 0.35μm CMOS process, a 32-bit phase-memory depth with 10-bit DAC The success of the compact DDFS streaming chip, its core area is 1.6mm2. At 3.3V power supply, the chip consumes 167mW and spurious-free dynamic range (SFDR) of 61dB.