论文部分内容阅读
功率UMOS结构相对于功率VDMOS结构的电压限制,通过对源漏沟道区掺杂不均匀的器件进行二维和两种载流子的数值模拟进行了比较;还对两种器件表面和体内的电场分布进行了比较;预估了UMOS由Si/SiO_2界面附近高电场强度引起的碰撞电离所导致的击穿电压下降现象。
Compared with the voltage limit of the power VDMOS structure, the power UMOS structure is compared by two-dimensional and two-carrier numerical simulations of devices with non-uniform doping in the source and drain regions. In addition, The distribution of the electric field is compared. The breakdown voltage of UMOS caused by the impact ionization caused by the high electric field near the Si / SiO 2 interface is estimated.