论文部分内容阅读
基于45 nm PTM模型,采用Hspice对基本逻辑门进行了仿真,并使用Matlab对仿真数据进行了三维延迟曲面拟合.在这些仿真基础上,建立了关于输入信号翻转时间ti、输出负载电容CL、阈值电压变化量△Vth的传播延迟tp和输出翻转时间to的计算模型.采用时延模型对基准测试电路ISCAS85-C17进行了计算,并将计算结果与Hspice仿真数据进行了对比.结果表明,在仿真范围(ti=0～100 ps,CL=0～2 fF,△Vth=0～50 mV)内,该时延模型计算值与仿真数据的相对误差在±10％以内.该模型及其计算方法可适用于大规模数字IC的可靠性设计.“,”The propagation delay of logic gate under the impact of NBTI had been thoroughly evaluated by Hspice,and then the 3D surface fitting on the data obtained from the 45 nm PTM had been carried out in Matlab.Based on these simulations,the propagation delay (tp) and the output slew rate (to) had been explored to be a function of input signal slew rate (ti),output load capacitance (CL),and the shift in threshold voltage (△Vth)caused by the NBTI.The benchmark circuit (ISCAS85-C17) had been analyzed on the basis of 45 nm PTM and the proposed degradation model.The calculated data and the Hspice simulated data were compared.The results showed that the calculated error was less than ±10％ (@ti =0～100 ps,CL=0～2fF,△Vth=0～50 mV) compared with the simulated data.The proposed model and the calculation method could be embedded into the reliability design of large scale digital IC.