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针对太空环境的实际应用,为了满足32bit数据纠二检四,选用(50,32)BCH缩短码来实现.为了克服BCH编译码电路硬件结构复杂、计算周期长的缺点,对BCH码的编码和译码过程进行了研究,提出了一种求共有表达式的贪婪算法,使编码器与译码中求伴随式部分并行化设计后面积开销最小.通过使用直接译码算法求错误位置多项式,并去掉了复杂的除法操作,提高了译码器的效率.在SMIC 130nm的标准CMOS工艺下进行综合,结果表明:编码器的关键路径延迟约为1.10ns,而译码器只需4.91ns.
In order to meet the practical application of space environment, in order to meet the 32bit data correctness check four, the choice of (50,32) BCH shortening code to achieve.In order to overcome the shortcomings of BCH codec hardware structure, long calculation cycle, the BCH code encoding and The paper puts forward a greedy algorithm to find the common expression, which minimizes the area cost after parallelization of the adjoint part of the coder and decoder.Through the direct decoding algorithm to find the error position polynomial, The complex division operation is removed and the efficiency of the decoder is improved.After synthesizing in SMIC 130nm standard CMOS process, the result shows that the critical path delay of the encoder is about 1.10ns, while the decoder only needs 4.91ns.