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设计了一种双电容结构时钟自举电路,分析了电路工作原理,用Cadence Spectre仿真器和0.35μm CMOS PDK进行电路前仿真和后仿真。仿真结果表明,设计的双电容结构时钟自举电路能使采样电路线性度达到110 dB以上,该电路已用于16位A/D转换器的设计并流片。经测试,采用该结构的16位A/D转换器的SFDR为96.25 dB(FS),信噪比为76.45 dB(FS)。
A double capacitor structure clock bootstrap circuit is designed. The working principle of the circuit is analyzed. The circuit simulation is performed before and after the Cadence Specter and 0.35μm CMOS PDK. The simulation results show that the design of the dual capacitor structure of the bootstrap circuit can make the sampling circuit linearity of more than 110 dB, the circuit has been used for 16-bit A / D converter design and flow sheet. Tested, the 16-bit A / D converter using this structure has an SFDR of 96.25 dB (FS) and a signal-to-noise ratio of 76.45 dB (FS).