A design for a CMOS frontend integrated circuit(chip) for neural signal acquisition working at wide voltage supply range is presented in this paper.The chip consists of a preamplifier,a serial instrumental amplifier(IA) and a cyclic analog-to-digital converter(CADC).The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a –3 d B upper cut-off frequency less than 1 Hz without using a ponderous discrete device.A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain.The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 d B and have an input-referred noise of 6.7 V rms integrated from 1 Hz to 5 k Hz.The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 k S/s.The measured effective number of bits(ENOB) of the ADC is 8.7 bits.The entire circuit draws165 to 216 A current from the supply voltage varied from 1.34 to 3.3 V.The prototype chip is fabricated in the0.18-m CMOS process and occupies an area of 1.23 mm2(including pads).In-vitro recording was successfully carried out by the proposed frontend chip. A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 d B upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 The ADC digitizes the amplified signal at 12-bits precision with the highest sampling rate of 130 k S / s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit d raws165 to 216 A current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-m CMOS process and occupies an area of ​​1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip.