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设计了一种应用于无线传感网系统的4位100 MS/s超低功耗电流舵D/A转换器(DAC)。为了满足系统超低功耗和高线性度的要求,在保证输出电压幅度不变的前提下,增加后级滤波器的输入阻抗来减小DAC的输出电流,使用均衡开关序列补偿电流源阵列中的梯度误差来获得高静态线性度。电路采用SMIC 0.13μm CMOS工艺实现,电源电压为2.5V/1V。实测结果显示,DAC的功耗仅为0.49mW,积分非线性(INL)和微分非线性(DNL)均小于0.02LSB。32MHz采样频率时,无杂散动态范围(SFDR)在整个奈奎斯特频带内均大于30dB;100MHz采样频率,9.9MHz/42.5MHz输出信号频率时,SFDR达到32.8dB/23.6dB,核心部分面积仅为0.2×0.23(mm2)。
A 4-bit 100 MS / s ultra-low-power current steering D / A converter (DAC) is designed for wireless sensor network system. In order to meet the requirement of ultra-low power consumption and high linearity of the system, the input impedance of the post-stage filter is increased to reduce the output current of the DAC while keeping the output voltage amplitude constant, and the balanced switch sequence is used to compensate the current source array Gradient error to obtain high static linearity. The circuit is implemented in a SMIC 0.13μm CMOS process with a supply voltage of 2.5V / 1V. The measured results show that the power consumption of the DAC is only 0.49mW, the integral nonlinearity (INL) and differential nonlinearity (DNL) are less than 0.02LSB. SFDR is greater than 30dB over the entire Nyquist band at a 32MHz sampling frequency; SFDR achieves 32.8dB / 23.6dB at a 100MHz sampling frequency with a 9.9MHz / 42.5MHz output signal frequency, with core area Only 0.2 × 0.23 (mm2).