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数字下变频(Digital Down-Conversion,DDC)是实现全数字接收机的核心技术之一。下变频包括混频和抽取两个关键模块,中频输入信号通过数字混频器变换到基带,并经抽取滤波器降低采样率,从而进一步减少后端实时处理的计算量。采用MATLAB对数字下变频模块进行性能仿真和高效的设计,给出优化的多级抽取滤波器设计结果;并结合基于软件无线电构架的BPSK通信体制,证明数字下变频算法稳定可靠,适用全数字接收机的设计要求。
Digital Down-Conversion (DDC) is one of the core technologies for implementing an all-digital receiver. Downconversion includes mixing and decimation of two key modules, the intermediate frequency input signal through the digital mixer to baseband, and the decimation filter to reduce the sampling rate, thereby further reducing the amount of back-end real-time computing. The simulation and efficient design of the digital down-conversion module are carried out by MATLAB, and the design results of the optimized multi-stage decimation filter are given. Combined with the BPSK communication architecture based on the software radio architecture, the digital down conversion algorithm is proved to be stable and reliable, Machine design requirements.