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模拟乘法器是实现有源功率因数校正(APFC)的关键模块电路。为了提高APFC电路的性能,在对目前一般芯片中普遍采用校正电路的THD(总谐波失真)较大,导致功率因数较低的原因进行分析研究的基础上,给出了一种高线性度的单像限模拟乘法器,该乘法器在经典的电路结构上加以改进,采用双极型和CMOS混合工艺设计,在德国XFAB工艺厂进行流片。仿真测试和流片结果表明,该乘法器消除了传统的APFC电路总谐波失真较大的缺陷,提高了功率因数,并且没有增加版图面积,具有较高性价比,适合嵌入在中小功率APFC芯片中使用。
The analog multiplier is the key module circuit that implements Active Power Factor Correction (APFC). In order to improve the performance of the APFC circuit, based on the analysis and study of the reasons why the THD (total harmonic distortion) of the correction circuit is generally used in general chips at present, and the reason of the low power factor is given, a high linearity Single-quadrant analog multiplier. The multiplier is improved on the classical circuit structure. It uses a bipolar and CMOS hybrid process design and is streamed at the XFAB process plant in Germany. The results of simulation and streamers show that this multiplier eliminates the large total harmonic distortion of traditional APFC circuit, improves the power factor, does not increase the layout area, has a high cost performance, and is suitable for being embedded in small and medium power APFC chips use.