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非相干的包络同步码跟踪环不依赖载波跟踪的相位特性,可以解决在信噪比非常低的条件下的本地扩频码和接收扩频码的码同步,进而完成扩频码的稳定跟踪。根据非相干的包络码跟踪环的原理,利用Verilog设计了一个完整的非相干的包络码跟踪环的电路。在设计过程中利用IP核中的乘法器、IIR滤波器、DDS数字频率合成器,简化设计难度并快速形成设计模块。在采用XilinxISE实现上述关键部分电路的设计基础上,同时利用SynplifyPro对设计模块进行了综合,并在Modelsim6.0中对电路进行了功能波形仿真,证明了设计的可行与合理性。这种解决方案相对常规方法既具有软件验证的灵活性,又具有硬件的执行效率。
The non-coherent envelope synchronization code tracking loop does not depend on the phase characteristics of carrier tracking and can solve the code synchronization between the local spreading code and the receiving spreading code under the very low signal-to-noise ratio, thus completing the stable tracking of the spreading code . According to the principle of non-coherent envelope code tracking loop, a complete non-coherent envelope code tracking loop circuit is designed by Verilog. In the design process using the IP core multiplier, IIR filter, DDS digital frequency synthesizer to simplify the design difficulty and rapid design module. Based on the design of XilinxISE to realize the above-mentioned key part of the circuit, SynplifyPro is used to synthesize the design module at the same time, and the functional waveforms are simulated in Modelsim6.0, which proves the feasibility and rationality of the design. Compared with the conventional method, this kind of solution has both the flexibility of software verification and the execution efficiency of hardware.