段高速缓存器加载是微处理器保护方式下多任务调度、虚拟段式存储器管理及指令集使用频度较高的部分。文中探讨了段高速缓存器加载的数据结构和定义 ,给出了保护方式下段高速缓存器加载算法 ,提出了用于段高速缓存器加载的保护测试单元的细胞群结构。最后 ,用 EDA工具SYNOPSYS对段高速缓存器加载算法的微程序和段高速缓存器加载的保护测试单元 RTL级的 VHDL描述进行了综合与仿真 ,验证了其设计的正确性与有效性 Section cache loading is a part of multi-task scheduling, virtual segment memory management and instruction set usage in microprocessor protection mode. In this paper, the data structure and definition of segment cache loading are discussed. The algorithm of loading the lower segment of the protection mode is given. The cell structure of the protection test unit for segment cache loading is proposed. Finally, the EDA tool SYNOPSYS is used to synthesize and simulate the VHDL description of the segment cache loading algorithm and the segment test cache loaded RTL level, which verifies the correctness and validity of the design