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本文就法国SN338数字地震仪瞬时浮点增益放大器中逻辑电路的设计依据、设计方法进行了较为详尽的讨论,并在此基础上提出了两条简化电路的设计方案。
In this paper, the design basis and design method of logic circuit in SN338 digital seismograph floating-point gain amplifier in France are discussed in detail. Based on the above, two design schemes of simplified circuit are proposed.