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介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性、自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5MS/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.
A high-linearity, 13-bit, pipeline A / D converter using a variety of circuit design techniques is introduced. These design techniques include the use of passive capacitor error averaging to correct for capacitive mismatch errors and the gain-boosting op amp to reduce Limited gain error and gain non-linearity, bootstrapping switch to reduce the on-resistance of the switch, and anti-interference design to attenuate noise from digital supplies. The circuit is implemented in a 0.18μm CMOS process, including pads The area is 3.2mm2. Under 2.5MHz sampling clock and 2.4MHz input signal, the obtained differential nonlinearity is -0.18 / 0.15LSB, the integral nonlinearity is -0.35 / 0.5LSB, the signal to noise plus distortion ratio (SNDR) is 75.7dB and Spurious Free Dynamic Range (SFDR) of 90.5dBc. The SNDR and SFDR were 73.7dB and 83.9dBc, respectively, for the 5MHz sample clock and the 2.4MHz input signal. All tests were conducted at 2.7V power supply, Power consumption (including pad drive circuit) corresponding to sampling rates of 2.5 MS / s and 5 MS / s is 21 mW and 34 mW, respectively.