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Serial RapidIO (SRIO) is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check (CRC). In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections.
Protections for SRIO packets are provided by the cyclic redundancy check (CRC). In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resources consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. , this improved receiving controller is considered applicable in high-performance SRIO interconnections.