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本文提出了一种使用FPGA实现误码率测试的设计及实现方法。该设计可通过FPGA内建的异步串行接口向主控计算机传递误码信息,也可以通过数码管实时显示一段时间内的误码率。文章先介绍了系统构成和工作流程,然后重点分析了关键技术的实现。
This paper presents a design and implementation of a bit error rate test using FPGA. This design can transmit the error information to the host computer through the asynchronous serial interface built in FPGA, and can also display the bit error rate in real time through the digital tube. The article first introduces the system structure and workflow, and then focuses on the analysis of the key technologies.