在0.18μm 1P6M CMOS工艺上实现了一款适应于光纤无线电系统的分数分频锁相环型频率综合器。锁相环环路由鉴频鉴相器、电荷泵、片外三阶低通环路滤波器、LC压控振荡器、正交I/Q高频除2分频器、可编程分频器、Δ-∑调制器组成。重点设计了宽线性调谐范围的压控振荡器、高性能的电荷泵和线性的鉴频鉴相器。测试结果表明,压控振荡器的频率调谐范围为2.16～2.65 GHz;锁定频率为2.35 GHz时,频偏1 MHz处的相位噪声为-120.9 dBc/Hz;带内相位噪声性能在频偏1 kHz时为-79.9 dBc/Hz,10 kHz时为-71.3 dBc/Hz;1 MHz处的参考杂散为-50 dBc,满足光纤无线电系统性能指标的要求。 A 0.18μm 1P6M CMOS process to achieve a fiber optic radio system adapted to fractional frequency PLL frequency synthesizer. Phase-locked loop loop frequency detector, charge pump, off-chip third-order low-pass loop filter, LC voltage controlled oscillator, quadrature I / Q high frequency divider 2, programmable divider, Delta-sigma modulator. Focus on the design of a wide range of linear tuning voltage-controlled oscillator, high-performance charge pump and linear phase frequency detector. The test results show that the voltage-controlled oscillator frequency tuning range of 2.16 ~ 2.65 GHz; the lock-in frequency of 2.35 GHz, the phase noise at a frequency offset of -120.9 dBc / Hz; band phase noise performance in the frequency offset 1 kHz -79.9 dBc / Hz at -71.3 dBc / Hz at 10 kHz and -50 dBc at 1 MHz, meeting the performance specifications of fiber-optic radio systems.