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本文针对在ＡＳＩＣ逻辑综合结构级优化中，去除冗余逻辑结构后，组合逻辑电路上可能出现的时间延迟不一致现象，导致时序混乱，使时序正常操作的限定条件不满足，这就需要重新安排和分配时序。本文分析组合逻辑电路的结构，提出了调整方法，应用二阶段线性规划方法求出最优解，为ＡＳＩＣ逻辑综合中时序的正常化提供了最佳方案。
In this paper, ASIC logic synthesis structure-level optimization, the removal of redundant logic structure, combinational logic circuit may appear inconsistent time delay, resulting in timing chaos, the timing constraints of the normal operation of the unsatisfactory, which requires rearrangement and Assign timing. This paper analyzes the structure of the combinational logic circuit, puts forward the adjustment method, and applies the two-stage linear programming method to find the optimal solution, which provides the best solution for the normalization of the timing in ASIC logic synthesis.