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提出一种ＭＰＥＧ－２视频解码器中解码控制的ＶＬＳＩ设计。这里引入了一些新的硬件设计方法，如：将宏块和块控制作为主要状态；采用桶形移位缓冲器进行码流的分解；将控制状态组织成层次结构等，从而完成了ＭＰＥＧ－２ＭＰ＠ＭＬ的实时解码功能。
A decoding control VLSI design in MPEG-2 video decoder is proposed. Here we introduce some new hardware design methods, such as: macroblock and block control as the main state; barrel shift buffer code stream decomposition; the control state into a hierarchical structure, etc., thus completing the MPEG-2MP @ ML real-time decoding capabilities.