集成电路CAD版图验证可从掩膜版图中提取电路图,从而与原设计的电路图直接比较或进行电路模拟.应该注意到,随着电路规模的增大,其电路模拟和比较的时间和空间要求变得难于被接受,因此提出了将电路图转换成逻辑图,以便在高层次上更有效地进行逻辑模拟和与原设计逻辑图的比较,LEXTOR(Logic Extractor)实现了这一设想. LEXTOR在算法上作了新的探索.(1)借鉴形式语言学理论,发展了一种统一的MOS门电路的组合生成及识别方法,即通过句法分析完成门电路的提取.若出现新结构的门电路,只需相应增加一些新的规则,而不必更改整个程序,克服了现有的拓扑同构法和路径搜索法在通用性方面的局限性.(2)研究和归纳了触发器拓扑结构的一些性质,独 IC CAD Layout Verification Circuit diagrams can be extracted from the mask layout to directly compare or simulate the circuit design of the original design.It should be noted that as the circuit size increases, the time and space requirements for circuit simulation and comparison vary So it is hard to be accepted, so LEXTOR (Logic Extractor) has realized this idea by converting the circuit diagram into a logic diagram to more efficiently perform logic simulation and comparison with the original design logic diagram at a high level. (1) Referring to formal linguistic theory, a unified method of generating and recognizing MOS gates has been developed, that is, syntactic analysis can be used to extract the gates.If there is a gate with new structure, only Some new rules need to be added accordingly without changing the whole procedure and overcome the limitations of the existing topology isomorphism method and path search method in generality. (2) Some properties of the trigger topology are researched and summarized, alone